EE 530 UCSD Analog Integrated Circuit Design Lab

DescriptionEE 530 Analog Integrated Circuit Design: Lab Assignment
Department of Electrical and Computer Engineering
San Diego State University
Spring 2023
1. Design a two-stage CMOS Op-Amp with the schematic provided below, where the
1st stage is a current-mirror loaded differential amplifier and the 2nd stage is a
common-source amplifier. You can use one ideal current source, IBIAS, from which
the bias currents of the stages are obtained via mirroring achieved by M8-M5-M7.
The mirrors do NOT necessarily have current gains of (1:1).
Target Design Specifications:
1. Single supply: = 3.2V
2. = 5pF.
3. DC Gain > 2000 V/V
4. Phase margin in unity-gain configuration > 45˚.
5. Common-mode rejection ratio > 80 dB
6. Input common-mode range > 0.5 V
7. Output voltage range > 2.5 V
8. Keep the power consumption as small as possible.
9. Minimum length of devices: Lmin= 0.5 μm.
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Use the simulator of your choice, perform .dc, .ac, and .trans analyses that demonstrate the
specifications above.
Report Requirements:
1. Hand calculations.
2. A table showing: (i) W/L (ii) IDS (iii) VOV (iv) gm, and (v) ro of all devices.
3. Circuit schematic view.
4. A table summarizing the target and achieved design specifications.
5. If there are design specifications not meeting the targets, comment on what the reasons might
be.
6. A conclusion that highlights what you have performed in this project along with a summary
(brief) of the important design choices you think helped you achieve the specifications
Project Evaluation Criteria:
1. Clarity and accuracy of hand calculations.
2. If/how many of the design specifications are met.
3. If/how many of the report requirements are met.
4. Report clarity and conclusion.
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